This invention relates to improvements in thin film transistors (TFTs), and more particularly to improvements in TFT devices with organic semiconductors.
Over the last decade, IC technologies have been proposed that use organic semiconductor thin film transistors (TFTs). The chief attractions of such circuits stem from the anticipated ease of processing and compatibility with flexible substrates. These advantages are expected to translate into a low-cost IC technology suitable for applications such as smart cards, electronic tags, and displays.
TFT devices are described in F. Garnier et al., Science, Vol. 265, pp. 1684-1686; H. Koezuka et al., Applied Physics Letters, Vol. 62 (15), pp. 1794-1796; H. Fuchigami et al., Applied Physics Letters, Vol. 63 (10), pp. 1372-1374; G. Horowitz et al., J. Applied Physics, Vol. 70(1), pp. 469-475; and G. Horowitz et al., Synthetic Metals, Vol. 42-43, pp. 1127-1130. The devices described in these references are based on polymers or oligomers as the active materials, in contrast with the amorphous silicon and polysilicon TFT structures that were developed earlier. The devices are typically field effect transistors (FETs). Polymer active devices have significant advantages over semiconductor TFTs in terms of simplicity of processing and resultant low cost. They are also compatible with polymer substrates used widely for interconnect substrates. Polymer TFTs are potentially flexible, and polymer TFT ICs can be formed directly on flexible printed circuit boards. They also have compatible coefficients of thermal expansion so that solder bonds, conductive expoxy bonds, and other interconnections experience less strain than with semiconductor IC/polymer interconnect substrate combinations. While metal-insulator-semiconductor (MIS) FET devices are most likely to find widespread commercial applications, TFT devices that utilize both p-type and n-type organic active materials are also known. See e.g., U.S. Pat. No. 5,315,129. S. Miyauchi et al., Synthetic Metals, 41-43 (1991), pp. 1155-1158, disclose a junction FET that comprises a layer of p-type polythiophene on n-type silicon.
Recent advances in polymer based TFT devices are described in U.S. Pat. No. 5,596,208, issued May 10, 1996, U.S. Pat. No. 5,625,199, issued Apr. 29, 1997, and U.S. Pat. No. 5,574,291, issued Nov. 12, 1996. With the development of both n-type and p-type active polymer materials, as described in these patents, complementary ICs can be readily implemented, as detailed particularly in U.S. Pat. No. 5,625,199.
A prominent advantage of these TFT devices is low cost, and efforts continue to further reduce cost. Forming conductor patterns in transistor structures by conventional techniques has long been recognized as a relatively high cost operation. The conventional techniques are typically subtractive techniques, i.e. they involve depositing a blanket conductive layer, forming a mask on the conductive layer, and xe2x80x9csubtractingxe2x80x9d unwanted portions of the layer. The alternative, additive processing, is inherently more efficient, involving depositing or xe2x80x9caddingxe2x80x9d material only where it is desired. The drawback to additive processing for microcircuits is that very fine lines are difficult to produce. A primary motive for making very fine features in semiconductor technology is to reduce device cost. Since TFT device technology already offers low cost, somewhat larger features may be tolerated. This is especially the case if the cost of TFr devices can be reduced further using additive processing.
Among the common additive approaches are screen printing, stencil printing, contact ink printing, and non-contact printing (e.g. ink-jet printing). These techniques use various forms of metal powders, and employ a variety of patterning methods using masks and patterned applicators. A more recently developed approach uses metal powders with metal organic decomposition (MOD) materials. In a preferred MOD process, the pattern is formed electrographically, e.g. by electrostatic printing, where the xe2x80x9cmaskxe2x80x9d is created electrically. A variety of electrostatic or electrographic methods are known in the art. Many of these use photoconductive layers with either a positive or negative electrostatic image formed using light to create charge in the image pattern desired or to discharge a blanket charged layer in the image pattern. This approach is attractive for simplicity, and also because the method does not require a 1 to 1 mask or pattern, as many additive processes require. In this description, techniques of this variety will be referred to generically as electrographic printing.
A wide variety of materials can be used with electrographic printing. The likely candidates for forming conductive lines in IC technology are the commonly used IC metals, Al, Cu, and Au, and compound conductors such as TiN. These base conductors can be converted to vehicles for electrographic printing in a variety of ways. Proposals typically involve making fine powders of conductive material. In electrographic technology, these are referred to as toners.
Mixtures of fine metal powders and organic compounds which decompose on heating have been developed recently for IC applications. This technology, which is sometimes referred to as MOD (for Metal Organo Decomposition) technology, has proven attractive for microcircuit fabrication. The basic method is described and claimed in U.S. Pat. No. 5,882,722 issued Mar. 16, 1999; and U.S. Pat. No. 6,036,889, issued Mar. 14, 2000. Methods for preparing suitable toners of these materials for use in electrographic printing are described in U.S. Pat. No. 6,153,348, issued Nov. 28, 2000. The electrographic method has been proposed specifically for use in making TFT devices. See U.S. Pat. No. 6,274,412, issued Aug. 14, 2001. Each of these patents is incorporated herein by reference for relevant details of MOD technology.
The primary conductor material described in these patents is silver. Silver has always been an attractive candidate for electrical device applications because of its very low electrical resistivity. However, silver is one of the best electromigrating materials known, which means that in the presence of electrical fields, it physically diffuses uncontrollably, causing serious problems in a microcircuit environment. Silver also corrodes relatively easily.
A similar situation prevails for copper conductors. Copper also has very low resistivity, but is not used with gold since Auxe2x80x94Cu is an unstable metallurgical system.
A drawback to MOD technology in general is that the conductors are deposited in a porous state. The curing process results in a degree of densification, but the final product has typically at least twice the bulk resistivity of the conductor. Moreover, the porous MOD deposited conductor is susceptible to corrosion, as well as electromigration. In addition, relatively high conversion temperatures (typically greater than 120 C.) are required to achieve reasonably high conductivity, which is not compatible with plastic substrates.
Another drawback to MOD technology, identified in general earlier, is the limitation on the feature size that the electrographic technique is capable of forming. Lines of tens of microns in width, with equivalent spacing, can be produced, and such features sizes are suitable for many elements in TFT technology. However, the most critical dimension for TFT devices is the source/drain spacing. This spacing determines the channel length that, for high frequency performance, is advantageously minimized.
The foregoing problems in forming TFT conductors using MOD technology have been largely overcome by the method of this invention. According to one embodiment of the invention silver source and drain base patterns are made using the MOD technique. After cure, the silver base patterns are plated with gold using an electroless plating process. In the context of MOD technology, the gold overlayer produces several advantages. Due to the porosity of the MOD deposited material, the electroless plating solution penetrates the silver base pattern and essentially eliminates the porosity and results in smoother electrode surface. Since gold has a resistivity even lower than that of silver, the resulting structure exhibits significantly improved conductivity over the relatively high resistance of porous silver made using MOD techniques. The gold overlayer also cures the problem of corrosion that occurs with a bare silver conductor. Finally, the gold overlayer may be used to effectively reduce the source/drain separation so that the channel length can be reduced and adjusted according to the thickness of the gold plating.
Copper base layers may also be used. In this case contact between copper and gold must be avoided. Therefore, a nickel barrier layer is deposited prior to deposition of the gold layer.